Resolving the Technical and Business Challenges of Getting Connected to the Internet of Things

Agenda - Presentation Abstracts

Agenda | Register


Multicore Keynotes for the Multitudes
Location: Magnolia Room
Accelerating Business Value and Outcomes with Data and Analytics

Countries, cities, industries and businesses around the globe are becoming digital to capitalize on the unprecedented opportunity brought about by the next wave of the Internet – the Internet of Everything (IoE). When people, process, data and things are connected there is an incredible opportunity to create new revenue streams, compete with disruptive competitors, and deliver better experiences, and new operating models to drive both efficiency and value.

Once connected, gaining business insights from data is top of mind for organizations today. Over 38% of the value to be realized with the IoE will be generated by insights from analytics. To harness the data that is massive, messy and everywhere, it is necessary to deploy analytics from the core to the edge to bring together both historical and new real-time data sources to generate unique and real time insights. In this session, Mala Anand will demystify big data and analytics and showcase how companies are benefiting today.

Accelerating Solutions for IoT

Today, the IoT revolution is transforming markets from a 'sale of goods' trade to a 'sale of goods and services' trade; economy. To fuel this model, intelligent and connected platforms will emerge to enable new value chains based on platforms and their associated ecosystems. These connected platforms will drive additional changes to markets by giving customers a direct line of communication to vendors, enabling consumers to provide specific use case information that lets vendors provide goods and services customized to individual consumers. Ali Sebt, President of Renesas Electronics America, will discuss how forward-thinking semiconductor vendors can better serve IoT customers by simplifying the design process to help them develop unique, connected applications that capitalize on the IoT economy.

Bridging the Physical and Virtual Worlds

From a technology perspective, bridging the physical and virtual world to accelerate IoT and help companies optimize and transform their businesses requires an end-to-end approach. This keynote will discuss the importance of achieving synergy between silicon and software to help companies integrate new technologies into existing legacy systems; explain how integrated, end-to end solutions bridge the intersections between information technology and devices; and provide insight into the supply/value chain and the ecosystem.

Designing for IoT: 5 Elements of Innovation for Success

IoT presents a vast number of opportunities for innovation across industries. While specific opportunities vary greatly depending on the industry and the application, IoT device design needs to address not just the complexities around connectivity, node based processing and sensor analytics, but also the evolving requirements of security and interoperability. Coupled with emerging standards and the flexibility that over-the-air updates and always-on devices provide, innovation options exist across all phases of a project lifecycle to allow extensions in use and purpose beyond the initial concept. In designing the next generation of IoT devices, where as an industry do we need to innovate to drive progress, and where as companies can we innovate to create our own differentiation?

Securing the Internet of Things: From Node to Cloud

As the IoT gains momentum, one challenge has become more evident - the lack of unified guidelines for ensuring security of IoT applications. The things on the internet are increasingly vulnerable to security breaches. Recently, execution of unauthorized code enabled the exfiltration of millions of credit cards and in another case, vital automotive systems were taken over by a hacker injecting rogue data into a car's controller network. Securing the IoT is a multi-faceted issue, encompassing platform trust, access control, and data security in systems spanning cloud data centers, networking processors, and sub-$1 nodes. A holistic view of the systems and challenges comprising the Internet of Things is needed for it to achieve its potential value and transform into the Internet of Tomorrow.


Unparalleled Multicore Strategies
Location: Cypress Room
At the Nucleus of the Hardware Software Explosion

Software engineers are under ever increasing pressure to quickly deliver flawless systems of ever increasing complexity while the requirements are constantly evolving. To this end the software engineer desires a simple system composed of one extremely fast processor with plenty of memory and very fast input and output. Hardware engineers are constantly being pressured to deliver more performance at lower cost and power. The result is Multicore systems which created the Multicore Software Crisis. The industry has done a lot to address these issues. We now have SMP, languages and APIs to help but work remains. In this paper we will compare and discuss the pluses and minuses of the leading solutions and identify a number of problems that are not yet being addressed.

Emerging Applications in Networking: To Multicore and Beyond

Emerging applications in Datacenter and Enterprise have an opportunity to leverage SoC’s with a large amount of multi-core processing with HW acceleration at their disposal. These applications include Software-Defined Networking (SDN), Software-Defined Storage, Network Function Virtualization (NFV), and Virtualized Infrastructure. Several interesting questions are emerging in this new age networking: Can these applications leverage multi-core processing? Where and how much HW acceleration should be included? How can applications harness these resources? We will discuss these questions and outline solutions based upon Cavium’s latest multicore processors addressing the needs in these emerging applications.

Single Core or Multi-Core? VISC: A New Architecture Wave & Microarchitecture Design Philosophy

Obtaining higher performance in microprocessors is very costly. One can trade-off more complex multi-threaded programming associated with simpler processor designs for the ease of programming associated with complex processors designs. Mohammad Abdallah, President and CTO of Soft Machines, will discuss the challenges of these two approaches to achieve higher performance. An analysis of the power, performance, area and complexity trajectories will be explored. A new architecture paradigm and microarchitecture philosophy for multi-core, VISC, will be presented as an alternative to the traditional ways of designing microprocessors, giving a deep insight into the characteristics that distinguishes this new architecture wave from its predecessors, CISC and RISC.

The Present and Future of Developing Embedded Multicore Systems

Companies have long recognized the benefits of multicore processors in a wide variety of applications. However, leveraging the performance of modern processors is only possible if the applications’ parallelism can be unlocked. In this strategy keynote, Tobias Schuele will outline the main challenges from an industrial perspective and describe solutions suitable for real applications. He will also present tools and libraries developed by Siemens in collaboration with research institutions that simplify parallel programming – leading to significantly improved reliability, performance, and productivity. Some of these libraries and tools are available as open source software and will continue to expand into the future.

Winners of Multicore Processors in Data Centers and Networking

The ability to scale performance is the foundation of software defined computing and networking. Instead of increasing clock operation, adding more CPU cores is the optimum way to scale processor performance, resulting in a rapid increase of multicore processors. Multicore processors must support SDN and have the performance to implement virtual network function. Vendors needs to provide support for open source software such as ODP. After reviewing the major trends in data centers and networking, this presentation will overview the multicore processors and highlight the successful vendors amongst the ARM, x86, and Openpower landscape.


Poster Sessions
Lessons learned from successful medical multicore software development

In order to benefit from progress in hardware, software development faces a paradigm change to parallelism. In the medical domain, this has even more impact. Certification of software is expensive. Therefore, reuse is mandatory and the life-cycle of software is much longer than that of hardware. To utilize the potential of multi-core systems, software architects are recommended to have a closer look on scalability, granularity and decoupling. For illustration of the lessons learned from successful multicore software development, examples are shown. Which and how design decisions contribute to sustainable solutions and a personal forecast of major trends are presented.

Runtime Analysis of Parallel Applications for Industrial Software Development

Utilizing the parallelism offered by multicore CPUs is hard, though profiling and tracing are established techniques to understand, debug, engineer, and optimize codes. While many tools are available to capture profiles and traces, these tools are often difficult to use in industrial contexts. Tool development often started with sequential codes to transition to parallelism not until later, resulting in improper feature sets and usability. In contrast, parallel tools are often targeted towards HPC. As this renders these tools less suitable for codes using alternative threading models (POSIX, Qt, and ACE), this talk presents extensions to the open-source tools Score-P and Scalasca. Score-P captures detailed execution data allowing Scalasca to perform an automatic performance analysis.


Applying Multicore Technology for Programmers and Engineers
Location: BayShore East
A Better Way to Convert Your Algorithms into Robust, Massively Parallel Code

The days of programming in a one-size-fits all language are quickly becoming a thing of the past, especially for multicore and many-core systems. This session will introduce SequenceL, the right tool for the multicore and many-core programming job that works in concert with C/C++, C#, Java, Python, etc. SequenceL is a compact, powerful functional programming language and auto-parallelizing tool set that quickly and easily converts algorithms to robust, massively parallel C++ (and optionally OpenCL) code. This Turing complete, domain-independent language was originally developed in partnership with NASA for applications in guidance, navigation, & control systems. It has since been applied in a variety of applications including video processing, audio processing, oil & gas, networking, etc.

Accelerate with ASIPs - Blending Performance and Efficiency with Programmability

Offloading performance or power-critical functions from merchant processors into specialized accelerators is commonplace in today's SoC designs. Most often these accelerators are implemented as fixed-function hardware. Using fixed-function hardware accelerators comes with a heavy cost, however - loss of software programmability. This is intolerable in today's business environment where the ability to quickly adapt IP blocks and SoCs (for evolving requirements) often drives the financial success (or failure) of entire development teams. Using examples from the wireless domain (including FFT), this presentation highlights how a powerful way to build accelerators that preserve their power & performance advantage, while retaining programmability. Hint: The trick is to use ASIPs.

Dangerous Assumptions in Multicore Programming

This presentation will describe some surprising ways in which code that looks correct can fail when used in a multi-threaded application. Unanticipated compiler optimizations can cause trouble even for programmers experienced with techniques to avoid data races. The talk will begin with a quick review of common concurrency bugs and standard approaches to avoiding them. It will then move beyond the basics and look at more subtle defects that result from reasoning based on flawed assumptions about compiler behavior. Attendees will leave with a better understanding of the types of constructs to avoid to ensure programs behave correctly. Techniques for finding concurrency bugs will also be explored.

Ease of Use for Heterogeneous Multicore SoC

There are well documented examples of Multicore processors that are no longer in use today due to their programming difficulty. Writing applications for heterogeneous Multicore processors is growing more difficult due to the added complexity associated with multiple core types, multiple accelerators and offload engines and vanishing visibility into the inner workings of heterogeneous Multicore processors. There are many methods available to help with this challenge including abstractions such as APIs, concurrency abstraction layers, virtualization, and operating systems, software driven hardware/software co-design techniques, development and debug tools, and programming languages. We discuss the best combination of techniques, processes, and approaches to achieve the right balance.

Evolution and Adoption of Industry Standards for Multicore Development

This session provides an update on two popular industry standards from the Multicore Association. We will review the SHIM specification, which was publicly released this year, and provide an overview on its adoption by companies and research projects and explain the open source tools to generate SHIM XML. We will discuss the development of MCAPI Version 3 which is focusing on standardized subsets, zero-copy messaging, safety critical support, channel functionality and MCAPI beyond multicore. The group is looking at broadening the scope from closely distributed computing to also include IoT communications, which is, in essence, multicore communications and a natural progression.

How to Apply DSP Acceleration for Power Efficient Compute

Heterogeneous computing is everywhere, from high performance computing (HPC) using heterogeneous architecture typically based on a combination of CPU's and GP-GPU's, to Microsoft's announcement of accelerating search with FPGAs. Heterogeneous SoC architectures with DSP offload and custom software solutions have been used in the embedded space for decades. OpenCL and OpenMP languages offer the opportunity to have the relative simplicity of programming a multicore CPU, while leveraging the power efficiency of more specialized compute engines such as DSPs. This presentation compares the power efficiency of implementing compute for example algorithms, such as basic linear algebra and FFT, on ARM cores using OpenCL to offload the compute intensive parts to a DSP.

Khronos Open Standards for Multicore Development - The State of the Union

The Khronos Group creates open, royalty free standards that enable developers to access advanced processor and acceleration capabilities. This session explores the Khronos APIs that are relevant to multicore programming, including OpenCL, OpenGL, OpenVX and the newly announced Vulkan and SPIR-V, and provides up to the minute insights and roadmaps for these enabling technologies.

Optimizing High Bandwidth Traffic on SoC

Modern SoC design is generally composed of a set of heterogeneous processing elements with conflicting traffic requirements. The high bandwidth that these devices require, forces SoC designers to consider multi-channel designs to achieve the bandwidth from DRAM. This session will explore the key issues with multicore accelerator traffic, contention at the DRAM and innovative approaches to solve the bandwidth paradigm.

The Automatic Parallelization of General Code for Multicore Processors

Rapid proliferation of multicore processors poses a major challenge, since their apps, embedded or not, must be parallelized to exploit the potential for speedups and reduced power. Most parallelization is performed via expensive manual methods or traditional automatic methods that do not perform well on general code written in popular programming languages, thus excluding vast amounts of single-threaded legacy code. Automatic parallelization of general code has not been possible due to a lack of precision or a unified theory. With a mathematical foundation based on a new signal flow algebra, a breakthrough in static analysis enables a highly scalable central process that untangles general code and identifies the independent pieces. Already parallelized code may be further parallelized.

Towards a Compiler Infrastructure for Heterogeneous MPSoCs: Lessons Learned and Case Studies.

Heterogeneous MPSoCs excel at delivering computing performance and controlling energy/power consumption demanded by today’s and future electronic products. The bottleneck to unleash the promises of MPSoC platforms shifts to the tedious, largely manual software development process. In this talk we present two case studies that demonstrate sequential code partitioning and optimal mapping/scheduling and automatic code generation. The first case addresses sequential code parallelization in the context of smartphone applications. In the second use case, system architects use a compiler infrastructure to drive power-aware software distribution for multicore devices.